Spin logic can enable a new class of computing circuits and architectures for the beyond Complementary Metal Oxide Semiconductor (CMOS) computing circuits and architectures. However, existing experimental demonstrations of spin logic devices suffer from low spin injection efficiency due to the requirement for an air break during the deposition of critical spin injection layers, and due to reliance on multi-angle deposition with a mask-in-chamber flow (where deposition is done with a non-contact mask, and where different geometries are obtained via multi-angle deposition). These existing processes suffer from low interface quality (i.e., interface quality is rough) and thus low injected spin polarization. These existing processes also suffer from the difficulty to integrate such processes into a High Volume Manufacturing (HVM) process.